60 GHz Examples


The aim of this research it to build a universal radio frontend, self healing RF circuits with Built In Self Test (BIST), and millimeter-wave circuits and systems from 30-300 GHz frequency range.

Current Trends in RF and Microwave Integrated Circuits Research (2)

FETs vs. HBTs

Fig. 1 Charge control principle in FETs and HBTs.

Before analyzing the two devices using  small signal models, it is important to compare their fundamental physical constructions shown in Fig. 1. In field effect transistors, the controlling charge resides on the gate, is of opposite sign, and is physically separated from the controlled charge which travels through the channel between the source and drain. Since only one type of carriers (electrons or holes) contributes to current flow in the active mode of operation typically employed in HF circuits, FETs are also described as unipolar devices. On the contrary, in HBTs, the controlling charge (holes in npns, electrons in pnps) is collocated in the base with the controlled charge (electrons in npns, and holes in pnps). This explains the bipolarnature of these devices. The second and third main differences between the two structures reflect the direction of current flow, and the technological control of the minimum feature size, gate length, L, and vertical distance between emitter and collector, for FETs and HBTs respectively. Intrinsic FET speed is therefore driven by lithography whereas HBT speed is determined by the precision with which we can grow thin semiconductor layers vertically, for example by atomic layer deposition techniques. Historically, vertical control of semiconductor layers has been several generations ahead of lithographic resolution and less costly to realize. However, as devices are scaled to smaller dimensions, 3D parasitics become dominant and limit real device performance. Therefore, the most advanced HBTs and FETs require scaling in both vertical and lateral dimensions. All the features discussed above are summarized in Table I.


Table I. Comparison of FETs and HBTs

Nanoscale MOSFETs show many bipolar-like features, such as gate leakage current not unlike the base current of the HBTs, exponential sub threshold behavior, similar output characteristics, and almost identical in form (although physically different) small signal and noise equivalent circuits. For the high frequency circuit designer, designing with either FETs or HBTs should be almost transparent.

Fig. 2 Small signal equivalent circuit of both MOS and HBT in high frequencies.

The high frequency small signal equivalent circuits of both nMOS and HBT devices is shown in Fig. 2. In the HBT at high frequency, Cπ is dominating the input impedance of the device and rπ can be omitted. And this reduces the equivalent circuit of the HBT to the equivalent circuit of the MOS device and one general small signal model can be used as depicted in Fig. 3. This small signal circuit is a good approximation for first order hand calculation and design. Then more accurate simulation with either BSIM 4 for CMOS or VIBIC & HICUM models for HBTs should be carried out for final design steps.

Fig. 3 general small signal equivalent circuit of both HBT and nMOS at millimeter-wave Frequencies.

60 GHz Transceivers Examples

60 GHz Communication Link Budget Calculations.

Prior to presenting highly integrated 60 GHz transceivers, 60 GHz communication system link budget calculation should be carried out. This will demonstrate why beamforming and phased array systems are of great interest in millimeter-wave communication systems.

Assuming that 1 dB compression point of the transmitter is 10 dBm and the noise figure of the receiver is 10 dB. Those are reasonable numbers for current silicon technologies (90 nm CMOS). The bandwidth is 1 GHz, this leads to – 74 dBm noise floor of the receiver. The path loss of 60 GHz signal is 68 dB for 1 meter distance.  For simple modulation such as FSK or QPSK the required SNR at the demodulator is from 10 to 14 dB. Using those numbers one can see that there is no link margin for fading or shadowing.

One solution for this problem is using highly directive antennas; this will enhance the link margin by the antenna gain in both sides TX and RX. Highly directive antennas are suitable for consumer electronics market specially WLAN and WPAN.  Here arises the need to develop phased-array transmitters and receivers working at mm-wave frequencies to provide high link gain without sacrificing angular coverage. The main advantage of the phased-arrays is that electronics beamforming and steering can be achieved. In transmitters, phased-arrays are used to increase the effective isotropic radiated power (EIRP), while in receivers, they are used to increase the signal to interference-noise ratio (SINR). Higher EIRP and SINR are translated into higher bit rate and longer distance.

Fig. 4 A generic beam forming system employs arrays of antennas and transceivers to boost gain, power, and sensitivity.

Phased array system can be defined as: Multiple antenna system, electronically change the direction of the beam, by introducing a phase shift and amplitude control for each element as shown in Fig. 4. Assuming that the transmitter will has 4 TX elements and the receiver has 4 receive channels. The link budget will increase by 18 dB (12 from TX and 6 from the RX). As a result the system will be more robust and high distance could be achieved.

Single Element Transceiver

Recently fully integrated 60 GHz transmitter and receiver have been presented in the literature. In this section an example of 60 GHz transmitter and receiver will be presented. Both transmitter and receiver are based on sliding IF architecture, in which one PLL or frequency synthesizer is used to drive both RF and IF mixers. This will eliminate the need of two local oscillators hence reducing the complexity of the chips. Fig. 5 shows the block diagram of both TX and RX.

Fig. 5 60 GHz TX and RX architecture

In transmitter, the 48 GHz output of the PLL is divided by 4 to generate 12 GHz I/Q LO signal to drive the IQ modulator. The differential baseband input are fed to the modulator through baseband VGAs. The output signal of the modulator is up-converted with the Gilbert cell mixer. The 60 GHz generated signal is then filtered using on chip integrated passive filter and fed to the power amplifier. The purpose of the filter is to attenuate both the image at 36 GHz and the VCO feed-through at 48 GHz. A strong feedthrough signal would affect the linearity of the receiver frontend, because the transmitter and receiver antennas are placed in close proximity. The Q-factor of integrated inductors for the 60 GHz range is low (typically 15 to 20), resulting in high insertion loss and limited selectivity. For a compact design, a lumped element filter type was chosen. The measured insertion loss is 3.3 dB at 60 GHz. The image rejection at 36 GHz is 27.7 dB. The VCO feedthrough at 48 GHz is attenuated by 12 dB.

The saturated output power of the power amplifier is around 20 dBm delivered to differential 100 Ω antennas. It consists of three stages of cascode amplifiers offering high gain around 30 dB @ 60 GHz. The PA layout is drawn symmetrically utilizing the ac ground for the differential signal at the symmetry line of the layout. The matching topology between stages is an L-C structure. The inductances were realized as lines in the top metal layer. They were bent in the layout in order to end at the symmetry axis to utilize the ac ground. The modulation scheme used for data transmission is OFDM which is sensitive to nonlinear distortion. This means that the PA has to be optimized for high output P1dB rather than for saturated output power. To achieve a high P1dB, a class A PA was chosen. The PA draws 190 mA from a 3.7 V supply. Full description and schematic of the PA is presented in ‎[1].

The receiver exhibits the same architecture; a differential architecture is adapted from antenna to baseband because of its robustness with respect to bond wires and its common-mode rejection ability. The quadrature LO signals for the second down-conversion mixers are generated by a divide-by-four circuit in the PLL chain, which gives perfect IQ signals because both I and Q signals respond only to the rising edge of the 48 GHz VCO output.

The receiver front-end consists of a low-noise amplifier (LNA), a mixer, a PLL and an IF demodulator. The LNA is a three stage common emitter amplifier with 18 dB gain and 22 GHz bandwidth. Its main design and implementation issues have been shown in ‎[2]. Minor modifications have been made to the LNA for technology and process migration. However, only the simulated overall noise figure was given in ‎[2] due to the lack of noise measurement. The 12 GHz demodulator is designed to have a conversion gain of 50 dB with more than 30 dB gain control range. An SPI is introduced for the gain and IQ VGA mismatch control, thereby reducing the number of bond pads. The complete receiver analogue frontend has a 78 dB conversion gain. The RX consumes 980 mW from two different supplies: 3.3 and 2.5 V.

PLL Synthesizer

The realization of an RF PLL at frequencies from 58.32 to 64.8 GHz is very challenging, especially for the VCO and the first frequency divider stage. Using a sliding-IF topology, the PLL frequency is reduced to 80 percent of these values. As a result, the following frequencies must be generated: 46.656 GHz, 48.384 GHz, 50.112 GHz and 51.84 GHz. If two VCOs selectable by a digital command are used, a VCO tuning range of 2.16×0.8=1.728 GHz plus safety margin is required. The feasibility of such a solution was first shown in ‎[3], where an integrated 48 GHz PLL in SiGe-BiCMOS with 2.4 GHz tuning range has been demonstrated. The PLL, unlike other TX and RX blocks, features both bipolar and CMOS transistors. The VCO and static dividers are realized with bipolar transistors, while the PFD and charge pumps employ CMOS transistors. The 48 GHz-band PLL is used to down-convert the 60 GHz RF signals to the 12 GHz-band. A sliding IF of about 12 GHz is generated from the 48 GHz VCO using a 1:4 frequency divider, which is used for the downconversion to

Fig. 6 Schematic of frequency synthesizer.

baseband with an I/Q demodulator. Fig. 6 shows the basic PLL architecture suggested in ‎[5]. The VCO output frequency is divided by four to generate quadrature signals at IF of about 12 GHz. This signal is divided by the programmable divider consisting of a 1:45 bipolar divider and a programmable low-speed CMOS divider. The phase-frequency detector (PFD) compares the 9.6 MHz signal of the divided crystal frequency with the divided VCO frequency. The PFD output is connected to a high-current charge pump (CP1) for VCO fine tuning and a low-current charge pump (CP2) for coarse tuning. The two parallel tuning loops allow a low phase noise, a low level of reference spurs and a large tuning range to be achieved simultaneously. The voltage divider at the output of CP1 keeps the dc voltage at the VCO fine tuning input roughly constant ‎[4], which makes the loop bandwidth fairly independent of device parameter variations with process, supply voltage and temperature (PVT). The total tuning range is defined by the slow coarse tuning loop, in which the noise of CP2 is almost eliminated by a large external capacitor. In this transceiver, a 48 GHz PLL as described in [2] contains only one VCO. An IEEE compatible PLL using an array of two VCOs has been tested successfully and will be included in a future design. The measured PLL phase noise at 1 MHz offset was -98 dBc/Hz ‎[3]. This corresponds to an integrated RMS phase error after baseband filtering below 1.5o, which is more than sufficient for 16-QAM OFDM transmission ‎[5].


In this article, we presented an introduction to the current research in millimeter wave integrated circuits. It also illustrates the new applications in which millimeter wave circuits and systems can be applied. Limitation and challenges for millimeter wave design in current silicon technologies are addressed. Finally a simple description of one of the state of the art 60 GHz transmitter and receiver is provided.

In the next articles we will focus on millimeter wave phased array systems from architecture to circuit implementation in silicon technologies.


[1]   Glisic, S.; Scheytt, J.C.: A 13.5-to-17 dBm P1dB, Selective High-Gain Power Amplifier for 60 GHz Applications in SiGe, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Oct. 2008.

[2]   Sun, Y.; Borngräber, J.; Herzel, F.; Winkler, W.: A Fully Integrated 60 GHz LNA in SiGe:C BiCMOS Technology, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM),Santa Barbara,USA, Oct. 2005, pp. 14-17.

[3]   Herzel, F.; Glisic, S.; Winkler, W.: Integrated frequency synthesizer in SiGe BiCMOS technology for 60 and 24 GHz wireless applications, Electronics Letters, 43 (2007), 154–156.

[4]   Herzel, F.;Osmany,S.A.; Scheytt, J.C.: Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs. IEEE Trans. Circuits Syst. I, Regular Papers, 57 (2010), 1914–1924

[5]   Herzel, F.; Choi, C.-S.; Grass, E.: Frequency synthesis for 60-GHz OFDM transceivers, European Conference on Wireless Technology (EuWiT2008),Amsterdam, 2008, pp. 77-80.

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