Analog to Digital Converter Architecture


In real world application, Most of the quantities surrounding us such as voices, images, pressure, temperature, etc.., are analog in nature. Processing of such signals, in its analog form, is difficult and costly which means that all analog signals need to be converted into digital signals.. ADC converts the analog signals.

Kasem Khalil

Department of Electrical Engineering, Faculty of Engineering

Assiut University, Assiut 71516, Egypt


Analog-Digital Converter

Analog-to-digital converter (ADC) is mostly commonly used in nearly all kinds of electronics. In real world application, Most of the quantities surrounding us such as voice, image, pressure, temperature, etc.., are analog in nature. Processing of such signals, in its analog form, is difficult and costly which means that all analog signals need to be converted into digital signals.. ADC converts the analog signals (voltages, currents) into its digital counterpart (normally binary), which will be processed by a digital signal processor (DSP) in electronic systems. The output of a DSP can be converted back into analog signal by using a digital-to-analog converter (DAC). so that people can see the image, hear the music, etc… Therefore, it is clearly that the AD/DA converters are indispensable parts and play important key role. It is like a translator connecting between the real world and the electronic devices. Regardless the evolving of electronics since the real world is analog, the AD/DA converters can never be disappeared. This may be the major motivation of researching and designing of AD/DA converters. Figure 1 shows how this AD/DA conversion process works. Application of ADCs are Conversion of audio signals (mobile microphone, digital music records, …), Conversion of video signals (cameras, frame grabber, …) and Measured value acquisition (temperature, pressure, luminance, …). In conclusion, the AD/DA converters are the indispensible interface between analog world and digital signal processors.

Figure 1
: AD/DA Conversion Process.


We describe a number of different conventional ADC architectures which can be used for specific application purposes. They are prominent by the number of clock cycles necessary or the sampling speed to perform the conversion of a single digital word and resolution. ADC architectures can be divided by the sampling speed into 4 categories: slow, medium, fast and oversampling as shown in figure 2.


Figure 2: Conventional ADC architectures categories.

Integrating ADC


There are two different realization approaches of the integrating ADCs: single and dual slope. These two types of ADCs operation are based on integration of a constant reference signal. Figure 3 consider first a single-slope ADC. The input signal is applied to the comparator positive input terminal, after being sampled with sample-and-hold circuit (S/H). The other terminal is connected to an integrator with constant reference voltage Vref, which is the ramp generator. When the input signal is larger than the integrated signal, the counter counts the clock cycles. When the integrator output voltage becomes equal to the input voltage, the conversion process is finished the comparator changes its state to zero. The input voltage is proportional to the number of clock cycles. However, it also depends on the integration constant, which can vary depending on matching of devices and the temperature. The accuracy of the single-slope ADCs also depends on the linearity of the generated ramp. To avoid dependency on the integration constant, double-slope architecture can be used. In this type of ADC, the integration is performed two times as shown in figure 4. The operation can be explained as follows; during the first phase, the input signal itself is integrated over Nref clock cycles, starting from some threshold voltage Vth. During the second phase, the integrator reference voltage is changed from Vin to −Vref and the second negative slope is generated. During The second phase integration is finished when the integrator output voltage is equal to the threshold voltage Vth. The ADC output value can be written as [2]:



The main drawback of both of these architectures is the long conversion time, which it is need 2NT for a single slope ADC, and 2N+1T for dual slope. Therefore, these types of ADCs can be use for low conversion rate applications. However, the conversion rate can be dramatically improved using a time-to-digital converter (TDC) as a time measurement device, resulting in conversion rates up to several mega samples per second [3, 4].

The main advantages of these types of ADCs are high resolution, low power consumption and small size [5]. For example, these advantages allow integration of these types of ADCs into each pixel of CMOS image sensors [6]. Another example can be their use in multichannel acquisition systems for nuclear measurements, where other types of ADCs result in unacceptable area and power consumption [3, 5].


Figure 3: Single slope ADC structure [1].

Figure 4: Double slope ADC structure [1].


Flash ADC


Flash converters can reach very high sampling rates since the only analog building block is the comparator. The flash ADC consists of 2N − 1 parallel connected comparators, each with a different reference level as shown in figure 5. The signal at the output of the comparators is a thermometer code representation of the input signal, i.e. it has 2N −1 bits corresponding to each comparator and each 1 show that the signal is above the corresponding reference level. A decoder is used to generate a more convenient representation at the output. The flash architecture allows obtaining an ADC with a very fast conversion time. At the same time, the flash ADCs with more than 8 bits are rarely seen [7]. The main reason for this is the exponential increase of the number of comparators as the resolution increases. The number of comparators increases exponentially with the number of bits, so each additional bit in resolution requires a doubling of the number of comparators.  As a result, the chip area and power consumption would be too large for higher resolutions. The chip area, power consumption and design complexity also increase for higher resolutions. The area increase leads to difficulties in comparator matching, and clock and signal distribution. Furthermore, the power dissipation per unit area in an IC is limited. This means that as the number of devices increases, the power consumption per single device should be minimized. This reduces the comparator bandwidth and analog bandwidth of the ADC as well. Finally, the last disadvantage caused by the large number of comparators is the large input capacitance as the large number of comparators is connected to the input signal bus. This also puts constraints on the sample-and-hold circuit (if used) and leads to undesired bandwidth limitation. To reduce the number of comparators, and as a result the input signal load capacitance, a number of interpolation techniques can be used [8].

The main part of the flash ADC is the comparator, and therefore its performance defines a large extent of the performance of the ADC. The comparator offset [9] is one of the parameter that limits the ADC resolution. The offset can be partly minimized by increasing the size of the input stage devices. This, however, leads to a larger input capacitive load. In order to minimize the offset averaging and auto-zeroing, techniques can be used in real time and discrete time ADCs, respectively, as well as special comparator structures [10].

The propagation delay is another important comparator parameter which can be defined as the time between the moment when the signal has been applied to the comparator input and when a correct decision is produced at the comparator output. This delay should be smaller than the sampling period. Failure to produce the result within the specified time can result in metastability, which leads to distortion of the sampled signal and makes it hard to recover the signal again. Whenever high conversion rates are required, Flash ADCs are used in these applications, for example: wideband RF and optical communication and video decoding.

Figure 5: Flash ADC structure [1].


Successive Approximation ADC


The successive approximation ADC consists of a comparator, digital-to analog converter (DAC) and successive approximation register (SAR) as shown in figure 6. The input signal is sampled with a sample-and-hold (S/H) circuit before the conversion takes place. After that, the SAR generates the first approximation by setting the MSB to 1, which corresponds to 0.5Vref. This digital word is converted into analog form by a DAC and compared with the input signal with the comparator. During comparison, if the input signal is larger than the digital approximation the MSB value is stored, otherwise the MSB is set to 0. After this, the same operation takes place for each bit in the SAR. After the last bit is determined, the SAR generates an end of conversion (EOC) signal, and the conversion is completed.

This type of ADC requires N clock cycles to perform one conversion, where N equals the number of bits. This latency limits the conversion speed of the ADC. Also, higher ADC resolution leads to a lower conversion rate. The conversion rate can be slightly improved by converting 2 bits in one clock cycle instead of one [11]. The ADC resolution is limited by the resolution of DAC, noise, offset of the comparator and sample and- hold circuit.

Using successive approximations, give us advantages as significant power savings can be achieved. Therefore, for applications where power constraints are tight but sampling rates are low, SA is particularly useful, e.g sensor nodes and medical applications. For this architecture due to low complexity and a small number of devices, the die area is relatively low as well.

Figure 6: Successive approximation ADC structure [1].

Pipeline ADC


A pipeline ADC employs a fully serial approach. It consists of a number of stages connected in series as shown in figure 7. Each stage of the pipelined ADC consists of a sample-and-hold circuit, ADC, digital-to-analog converter (DAC), a subtractor and gain stage. The analog signal is sampled with sample-and-hold circuit and is then split into two paths. In one path, the signal is converted with an ADC, to produce digital word and then converted back to the analog form with the DAC. This signal is then subtracted from the other path which is the original signal, to produce a residue and the first stage produce most significant bit (MSB). The residue is amplified, with gain G, and fed to the next stage where all stages are working in this way. This way, the analog signal is transformed into the digital form in M steps, starting with most significant bits which results in a latency in the beginning of the conversion procedure. The last stage contains only a sub-ADC and outputs the least significant bit (LSB). The requirements are higher for the first stage [12], both in terms of conversion accuracy and noise.

The pipeline architecture gives relatively high conversion rates and resolution, although its conversion rates are lower than for flash ADCs. Power consumption and area reduction can be achieved in the pipeline ADCs through amplifier sharing between stages [12, 13].

In high conversion rates applications such as in imaging systems [12], radio receivers [14], etc, pipeline ADCs can be found, and it can be used for medium to high resolutions.

Figure 7: Delta-sigma ADC structure [1].

Delta-Sigma ADC


The delta-sigma is an oversampling ADC, which means that the sampling frequency is much higher than the one defined by the Nyquist criteria. It is also called a noise-shaping ADC. Figure 7 shows the block diagram of Delta-Sigma ADC. It consists of several blocks: the anti-alias filter, integrator, quantizer, DAC and digital output low-pass filter (LPF). The output from the quantizer is fed back to flow through the DAC and subtracted from the input signal; this feedback structure is called delta-sigma modulator. In this way, the integrator accumulates the difference between the analog input signal and its digital representation, minimizing this difference by the feedback loop. Another advantage of the feedback also separates the signal transfer function (STF) and quantization noise transfer function (NTF). The STF usually has low-pass characteristics and the NTF is high-pass. According to these bands, the quantization noise is pushed out from the signal band to higher frequencies; hence it is called noise shaping. The decimation filter at the output of the ADC filters the quantization noise outside the signal band. Another function of the decimation filter is to reduce the output data rate.

The actual analog-to-digital conversion is performed by the quantizer. The quantizer can be one bit or more. Multibit quantizers may require multibit DACs, which can limit the linearity of the whole ADC.

Single feedback-loop delta-sigma ADC is shown in Figure 8. Higher orders can be achieved by adding more feedback loops. However, there are stability issues to ADCs with higher than second order, which can be overcome by cascading several first-order or second-order modulators [15]. Each order N adds N + 1/2 bits for each doubling of the sampling frequency. This means that 1.5 bits per doubling of the sampling frequency can be achieved for the first order delta-sigma ADC, 2.5 bits for second order, etc. This can be compared with the previous result for Nyquist rate converters, where each doubling of sampling frequency gave only 1/2 additional bit of resolution. The integrator can be implemented either as continuous- (CT) or discrete-time (DT). The continuous-time integrator has advantages over discrete-time: higher sampling rate, inherit anti-aliasing filtering [16] and lower power consumption. The latter allows avoiding high order anti-aliasing filters, thus reducing die area and power consumption. However, ADC with CT integrators is more sensitive to clock jitter.

The main advantage of delta-sigma ADCs over Nyquist rate ADCs is that it does not require high precision analog components. This requirement is relaxed because high resolution is achieved by oversampling. This, however, also limits the delta-sigma ADC to medium frequencies application, where without need for extremely high clock speeds; high oversampling ratios can be achieved. Decreasing the oversampling ratio can make the ADC sensitive to the nonlinearities of its analog components. This limitation, however, can be overcome by using a feed forward technique.

Figure 8: Delta-sigma ADC structure [1].





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