Warning: count(): Parameter must be an array or an object that implements Countable in /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/post-template.php on line 259

FPGA-911

Summary:  

In this series we will try to get you through successful design with FPGAs while will highlight different design methodologies and guidelines to help you efficiently use FPGA in your next design.

This Series

 

FPGAs or field programmable gate arrays are an attractive solution for many design challenges. The adoption of FPGA in newer designs is increasing rapidly and it’s significantly compared to number of successful new ASIC designs and the total growth in semiconductors market.

Market for Standard Cell ASICs, ASSPs, and Programmable Logic IBS, Inc., “System IC Market Trends” (Q2/2010 Global System IC Industry Service), August 2010

In this series we will try to get you through successful design with FPGAs while will highlight different design methodologies and guidelines to help you efficiently use FPGA in your next design.

Programmability

 

FPGA or field programmable gate array is a programmable device just like traditional microcontrollers and processors. A designer just needs to translate his design requirements into chunks of code segments, integrate them, simulate, debug, compile and then download to the device to test or run the design.

The difference between a MCU and FPGA is “what is programmable?” MCU is a fixed structure that can execute a fixed set of pre-defined operations (instructions). Designer needs to translate his design into a list of those operations executed in a way to implement the required behavior of the design. It’s the order of those operations and the flow of data that differentiate one design from another and do the required job.

Unlike MCU, FPGA has a programmable structure. The idea is to be able to alter what the hardware can do not what the hardware should do.

MCU built to be as generic as possible to cover a range of applications possibilities. One can split all MCU available in the market into different categories according to the applications that those controllers are best fit. A vendor of MCU cannot meet the requirements of all market segments in a single device. Some of market segments require a super performance while others need MCU with minimum power consumption or the cheapest MCU. All or some of those requirements can conflict with each other and this is why it’s impossible to have a single MCU that can do everything and everywhere. In the market a MCU that targeting industrial applications can totally differ than a MCU that targeting telecommunication industry. The difference can reach the whole architecture not only a set of peripherals.

The main drawback of this is that designers need to learn many and different design environments, processors architectures, debugging and verification tools, software libraries, operating systems, etc. Even if designer is not shifting his or her job in different market segments, he or she may need to learn new tools and processor architecture for a new design in the same market segment. This leads to reducing ROI and increasing time to market.

FPGA made to solve such issues and many other issues in embedded system designs using regular MCU.

Fig.1 ASICs, Microcontrollers, and FPGAs Functional Comparison

Methodologies

 

Design with FPGA is basically a kind of digital logic design. The designer needs to translate his architecture into a mix of state machines, logic circuits, memories, registers, etc. which requires good understand of underlying architecture of FPGA.

Some of FPGA design methodologies adopted higher level of abstraction in which the designer can model the system using high level languages like Matlab or C or even using a graphical model. Then a specialized compiler can translate this model to a synthesizable RTL code. This methodology was first defined as Electronic System Level (ESL) design by Gartner Dataquest, a EDA-industry-analysis firm, on February 1, 2001.

ESL mainly depends on a set of predesigned library of primitive models like RAMs, ROMs, shift registers, processors, state machines, encoders, decoders, math functions, etc.  The designer should utilize those primitives in his design with limited configuration possibilities. The final results mainly depend on the capabilities of the compiler to merge down this model to the minimum set of FPGA primitive slices. ESL methodology still not adopted in wide scale in the industry as it not giving the optimum results of professionally hand-written code.

Fig.2 Example of ESL design flow using commercial design package from Binachip, Inc.


Even if you are happy with the results of ESL based tools, you still need to take the decision of which FPGA to use in a certain design. Selecting a device for a design depends on the understanding of your design requirements, possible future updates and features, and how this will translate to the infrastructure of a FPGA device. Again you need to master the device architecture and learn how specific device architecture can fit with your design requirements.

The good news that newer generations of FPGA are mostly built on the same technology but differ in terms of performance, cost, pin count, and resources count. An example of this is the 7th series of Xilinx FPGAs. This will reduce the time selecting a device for every new design.

Structure

 

FPGA have a programmable structure. In the heart of this structure is programmable interconnection matrix and configurable logic slices. This programmable structure is surrounded by programmable input/output blocks.

Fig.3 FPGA Structure


 

Understanding this structure and its capabilities will help you to effectively translate your design to a synthesizable logic on this structure. Unlike ASIC design, in FPGA you are limited to the capabilities of the configurable logic cells and the interconnection between them. You cannot pack a bigger logic circuit in a physical location than the configurable blocks can handle.

This is one cause of performance degradation in FPGA designs over similar ASIC designs. For instance a simple decoder circuit can run much faster in ASIC implementation than FPGA implementation, why?

Answer:

Inside configurable logic blocks there are programmable Look-Up Tables or LUT. LUT is the primary method to implement Boolean functions in FPGA.

Fig.4 Example of Configurable Logic Cell.

We can consider LUT as single bit ROM. The depth of that ROM depends on number of possible inputs to LUT. Today’s FPGAs are based on 4 or 6 input LUT technology. 4-input LUT can implement any 4 input Boolean function. For example:

Fig.5 4-input Boolean function implementation in Xilinx Spartan-3E device.

So what is the case if we need 5-input Boolean function? For example:

 

 

Fig.6 5-input Boolean function implementation in Xilinx Spartan-3E device.

Increasing the width of input enforces the synthesizer to split the function into multiple LUTs and then combine those using additional LUTs or multiplexers.

Every LUT has an intrinsic constant delay regardless the complexity of the function it implements. Splitting larger functions in many LUTs creates multiple logic levels and the total delay increases as the number of logic level increases too. Additional to delays in the logic cells, there are delays in the routing between them and this is the killing factor in FPGA if you are seeking a higher performance. Routing delays are very significant especially in large logic functions when the design must spread over large areas of the same FPGA die.

In ASIC the situation is bit different as wider Boolean functions can be implemented using custom logic cells and minimizing routing delays by physically locate those cells very close on the die.

The solution to such issues is design dependent. Some designs can adopt pipelining in logic functions implementation breaking down the total delay into multiple clock cycles (the same concept of instructions pipelining in microprocessors). In other designs we can manually place and route logic implementation in tight areas inside FPGA. In either of both solutions we must first try to optimize the functions for best implementation on FPGA.

Next

In next episodes of this series we will introduce different FPGA features and discuss the effective utilization of them. We will provide valuable design tips for those planning to use FPGA in a real design. Also we will introduce design methodologies in more details.

Muhammad Abdel-Ghany

Founder & Chairman of Luxor Instruments

Related posts:

 

  • Fatal error: Uncaught Error: Call to undefined function ereg() in /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-content/themes/VLSIEgypt/functions.php:28 Stack trace: #0 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-content/themes/VLSIEgypt/functions.php(44): commenter_link() #1 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/comment-template.php(1810): custom_comments(Object(stdClass), Array, 1) #2 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/class-wp-walker.php(147): Walker_Comment->start_el('', Object(stdClass), 1, Array) #3 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/comment-template.php(1777): Walker->display_element(Object(stdClass), Array, '5', 0, Array, '') #4 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/class-wp-walker.php(373): Walker_Comment->display_element(Object(stdClass), Array, '5', 0, Array, '') #5 /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-includes/comment-template.php(2126): Walker->paged_walk(Array, '5', 0, 0, Array) #6 /customers/9/c/6/vlsi in /customers/9/c/6/vlsiegypt.com/httpd.www/home/wp-content/themes/VLSIEgypt/functions.php on line 28