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PIN Photodiodes in Nanometer CMOS Technology

A huge increase in data traffic has been occurred for the past years due to the rapidly growing demand for higher data rates in telecommunication networks. The optical fiber can facilely deal with these large volumes of data. Optical fiber links provide superior performances to conventional electrical links in terms of bandwidth, channel loss, electromagnetic interference, reflection, and crosstalk. The III-V materials have been dominantly exploited for high-speed optical receivers but it is an expensive solution compared to the CMOS technology. Deep sub micron CMOS technologies have been rapidly advanced, enabling the implementation of several gigahertz integrated optical receiver. In particular, low-cost silicon CMOS optoelectronic integrated circuits (OEICs) become very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnect. Fully integrated optical receivers with integrated silicon photodiodes provide advantages over hybrid-implementations, including low-cost, reduced parasitic capacitance, and no bond-wire inductance.
Unfortunately, the optical absorption coefficient of silicon is quite low at 850 nm. Calculations using the standard photo-generation equations show that the penetration depth of light in silicon is 16.5um at 850 nm. In standard CMOS technologies, the silicon substrate is much thicker (hundreds of um) than penetration depth. Secondly, the doping concentration of silicon layers in CMOS technologies are typically quite high, and hence higher bias voltages are needed to deplete the active silicon layers. On the other hand, due to the high doping concentration, breakdown voltage of PN junctions in CMOS are fairly low, which limits the applicable reverse bias voltage on the integrated PDs.
Unfortunately, technology scaling has a negative effect on the photodiode performance. As technology shrinks, more metal layers are provided to be able to connect all transistors in a compact way. The transmission coefficient drops quite drastically for technologies with shrinking minimal line widths. The increased doping levels and lower nominal supply voltages also have a negative effect on the photodiode performance. The width of the space charge region decreases, as a result the drift current decreases, increasing the diffusion current, increasing the recombination and increasing the parasitic photodiode capacitance for a certain photodiode area. Consequently, the optical as well as the electrical performance becomes worse.
Recently, silicon PDs integrated in standard CMOS technologies have been demonstrated with multi-GHz bandwidth and gigabit- per-second (Gbps) data rate at near-infrared wavelength. A vertical PIN PDs using DNW with an active area of 70umx70um fabricated in a standard 0.18um CMOS process achieved 2.2GHz -3dB bandwidth with 0.24A/W responsivity at 850nm. A vertical PIN PDs using DNW with an active area of 50umx50um fabricated in a standard 0.18um CMOS process achieved 8.7GHz -3dB bandwidth with 0.018 A/W responsivity at 850nm . The CMOS-APD was designed and fabricated with 65-nm standard CMOS technology without any process modification. It can be realized without violating any design rules for the CMOS process technology. It includes shallow trench isolation (STI) between P+ and N+ regions, which prevent premature edge breakdown. An optical window having the area of 30μm by 30μm is formed by blocking the salicide process. It achieves the responsivity of 2.94 A/W and 3-dB bandwidth of 3.2GHz at 850nm.
A vertically stacked integrated triple-junction photo-detector(N+/ P-Well/ deep N-well ), fabricated in standard 90nm CMOS technology with an area of 80umx80um was designed and explored in the wavelength range from 400nm to 900nm. Measurements show that the 3 dB-cutoff frequency of the N+/ P-Well top diode was at 264 MHz and a responsivity of 0.03A/W at 750nm.

Dr.Mohamed Atef

Assistant Prof. Assiut University, Egypt

moh_atef@aun.edu.eg

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