Japan EDA Insight 2


As we set in our first article, Japan EDA Insight will focus on an Insight “small piece of information” topics that vary from the Educational System in Universities, Research Organizations, Design Tools, Hardware Platforms, and many other EDA trends, based on my experience living and studying in Japan, which I truly hope that VLSI-Egypt magazine readers find useful and interesting. In this article I would present one of most powerful tools in processor design which my Prof. Masaharu Imai architected thorough years of effort and collaboration from different lab members and ended in a spin out as a commercial tool known as ASIP Meister – An EDA tool for drastically reducing the design time of Application Specific Instruction Set Processors (ASIP). I would mainly reference the company web site located at http://www.asip-solutions.com/en/asip_meister.html and conference publications to introduce this tool to VLSI-Egypt magazine readers.

Different Processor Technologies

Processor technologies vary in their customization for the problem at hand, so assume that you have the functionality described by the program in Figure 1. You can typically design a processor which exactly do this functionality and nothing else (we call this Single Purpose Processor – note the shape match), a processor driving a baby bear toy hitting a drum is one example. Or, you can design a processor that executes the desired functionality and extends this to all problems with same nature, we call them Application Specific Instruction Set Processors (ASIPs), a Digital Signal Processor (DSP), a Vide co-processor and a Micro Controller are examples of these kind of ASIPs. Or, you can design a processor that executes any kind of problem at hand (note again the shape) and these are desktop/laptop processors or what we call General Purpose processors.

In depth, the main difference is in the architecture of the computation engine used to implement the desired functionality. For a single purpose processor, as shown in Figure 1, it contains only the components needed to execute a single program – you would find just few registers and a fixed control logic with a small data memory and no program memory, its merits are speed, low power and small die size. For an application specific processor, you would have an optimization for a particular class of applications having common characteristics as we stated, so you would find more registers, a program memory with Instruction Register (IR) and Program Counter (PC), a separate Data/Program memory and a custom Arithmetic, Logic, and Shift unit (ALU) with special functional units that solve specific application domain computations (signal processing, multimedia, control oriented). Its merits are more flexibility, good performance, size and power. On the other hands, the general purpose processor has a general purpose data path with large register file and general ALU, it has programmability using a Program/Data memory and IR/PC registers as ASIPs, its merits are high flexibility and high computation power.



Figure 1. Different Processor Technologies – A Simple View


Now, after we have understood the main concept behind an ASIP, let’s introduce ASIP Meister (Master in German).

Figure 2. ASIP Meister Design Flow

ASIP Meister generates dedicated processor hardware descriptions and software development tools automatically based on target processor specifications. You can easily get high flexibility for processor design only by modifying the processor specifications on user friendly ASIP Meister GUI.


Design Flow with ASIP Meister*


Lets’ summarize, the design flow with ASIP Meister (A Snapshot is shown in Figure 3) is as follows:


1. Set the design goals & architecture parameters of the target ASIP, such as the number of pipeline stages and instruction/data bit-width.

2. Select the hardware resources of the ASIP from (Flexible Hardware Model) FHM database library and set parameters for each resource.

3. Define ASIP storage specification & I/O interface.

4. Define the instruction type, format and exception information.

5. Check design quality with architecture-level estimation.

6. Describe the behavior of each instruction using ANSI-C like syntax.

8. Describe the micro-operation of each instruction per pipeline stage.

9. Check the performance with the generated HDL descriptions and software development tools.


For more details, I would recommend to go to Japanese site of ASIP Solutions and use google translate (I see good translation results!!!)




Generation of HDL Description

M. Itoh, S. Higaki, J. Sato, A. Shiomi, Y. Takeuchi, A. Kitajima, M. Imai, “PEAS-III: An ASIP Design Environment,”

2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp.430-436, September 2000.


Software Tools Generation

S. Kobayashi, Y. Takeuchi, A. Kitajima, M. Imai, “Compiler Generation in PEAS-III: an ASIP Development System,” Proc.

of SCOPES 2001, March 2001.


Figure 3. ASIP Meister: An ASIP Design Environment



Lessons To Learn


In my opinion Japan’s, leading in embedded systems since the early days lies in the strong knowledge in (1) Processor design – we have many companies which developed their own processors SH/SuperH family from Renesas, M32R from Mitsubishi, etc. and still prefers to use over ARM/Intel based processors (2) Real Time Operating Systems – ITRON is a national project that aims to be in all embedded systems sold in Japan from vending machines (Jidohanbaiki), automotives, etc. and its evolution now lead to T-Kernel/T-Engine projects which are main corner-stones in Ubiquitous Japan (3) FPGA prototyping – as an economic way to spread IP design culture among students (4) Applying this knowledge in commercial embedded systems on large scale with government support to give preference to indoor embedded systems.


Mohamed AbdElSalam is a Technical Lead for the Mentor Graphics Emulation Division (MED) –Egypt. He received his M.S. Degree from Ain-Shams University, Cairo, Egypt, and Doctor of Information Science and Technology from Osaka University, Osaka, Japan. He joined Mentor Graphics 1998-2002 in CSD, DCS-HDS, and again in 2008 to present in MED’s iSolve Group, working on hardware emulation targets for USB/SATA/Processors, VirtuaLAB and Transaction based Solutions



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